1. Field of the Invention
The present invention relates to a semiconductor memory including a sense amplifier and, more particularly, to a technology for securely reading out data which is written in a memory cell.
2. Description of the Related Art
In a semiconductor memory such as DRAM, data (charge) which is written in a memory cell leaks in a substrate and the like and disappears over time. Hence, the DRAM, for example, carries out refresh operation by rewriting the data in the memory cell at regular intervals in order to compensate a decrease in an amount of the charge in the memory cell.
In the DRAM, read operation and writing operation are generally carried out by using two bit lines (bit line pair). In the read operation, for example, reference voltage is first supplied to the bit line pair (precharge operation). Next, the data (storage charge) which is held in the memory cell is transmitted to one bit line. The storage charge in the memory cell is shared according to an amount ratio between the memory cell and the bit line, whereby voltage of one bit line changes. The voltage is compared with voltage of the other bit line (reference voltage), and xe2x80x9cH dataxe2x80x9d or xe2x80x9cL dataxe2x80x9d is read out.
Supposing that a state in which the charge is accumulated in the memory cell is xe2x80x9cH statexe2x80x9d and a state in which the charge is extracted from the memory cell is xe2x80x9cL statexe2x80x9d, the memory cell in the H state changes to the L state over time, as described above. For this reason, a difference between the voltage of one bit line to which the charge in the H state is transmitted and the voltage of the other bit line (reference voltage) decreases as time passes. Meanwhile, the voltage of one bit line to which the charge in the L state is transmitted is grounding voltage in general, and hence a difference between this voltage and the voltage of the other bit line (reference voltage) does not change even after the passage of time. Therefore, a read margin in the H state is smaller than a read margin in the L state. In other words, the memory cell in the H state is difficult to read out as compared with the memory cell in the L state.
Recently, a sense amplifier with improved read margin in the H state has been developed in order to eliminate the disadvantage like the above. In this sense amplifier, the voltage of one of the bit lines out of the bit line pair is forced to change by using a coupling capacitance which is connected to the bit line, immediately before the accumulated charge of the memory cell is transmitted to the bit line.
Since operating voltage of the semiconductor memory such as the DRAM has been decreased, it has been difficult to keep an enough voltage difference between the bit line pair and to operate the sense amplifier without fail. For this reason, a method of increasing the voltage difference between the bit line pair in the read operation by using the coupling capacitance which is connected to the bit line is indispensable to the recent DRAM.
FIG. 1 shows a principle part of DRAM to which this kind of sense amplifier is applied.
A sense amplifier 10 is connected to a bit line pair BLT, BLC. The bit line pair BLT, BLC are connected to memory cell arrays 14 via isolation gates 12. The isolation gates 12 on the left side of the drawing are controlled by a bit line control signal BTLP. The isolation gates 12 on the right side of the drawing are controlled by a bit line control signal BTRP. In the read/write operation, one of the memory cell arrays 14 on both sides of the drawing is connected to the sense amplifier 10 by the bit line control signals BTLP, BTRP.
The memory cell array 14 includes a plurality of memory cells MC. Each of the memory cells MC consists of a capacitor for storing the data and a transfer transistor for connecting the capacitor to the bit line BLT (or BLC). In this example, a gate of the transfer transistor of the memory cell MC which is connected to the bit line BLT receives a word line signal WLT. A gate of the transfer transistor of the memory cell MC which is connected to the bit line BLC receives a word line signal WLC.
The sense amplifier 10 includes a latch 10a, capacitances 10b, 10c made of nMOS transistors, write switches 10d, 10e and read switches 10f, 10g. The latch 10a consists of two of CMOS inverters with these inputs and outputs connected to each other. The latch 10a is activated or inactivated according to a sense amplifier activating signal which is not shown. A source and a drain of the capacitance 10b are connected to the bit line BLT and a control signal BLPLTN is received at its gate. A source and a drain of the capacitance 10c are connected to the bit line BLC and a control signal BLPLCN is received at its gate.
Either source or drain of the write switch 10d is connected to the bit line BLT and the other of the source or drain is connected to an input/output node ND01 (data bus). A write control signal WSELP is received at its gate. Either source or drain of the write switch 10e is connected to the bit line BLC and the other of the source or drain is connected to an input/output node ND02 (data bus). The write control signal WSELP is received at its gate.
Either source or drain of the read switch 10f receives a read control signal RDRVN, the other of the source or drain is connected to an input/output node ND03 (data bus) and its gate is connected to the bit line BLT. Either source or drain of the read switch 10g receives the read control signal RDRVN, the other of the source or drain is connected to an input/output node ND04 (data bus) and its gate is directly connected to the bit line BLC.
In the sense amplifier 10, currents passing through the read switches 10f , 10g vary according to the voltage difference between the bit line pair BLT, BLC. Voltages (amplification voltage) are generated in the input/output nodes ND03, ND04 according to the difference of the current, and the generated voltage is transmitted to a read amplifier and the like. Namely, the read switch 10f (or 10g) has a function of amplifying read data which is transmitted to the bit line BLT (or BLC). This kind of circuit system is generally referred to as a direct sense system. The sense amplifier of the direct sense system does not connect the bit lines BLT, BLC and column switches 16c, 16d directly. For this reason, the voltages of the bit lines BLT, BLC do not change by the operations of the column switches 16c, 16d. That is, even when a column selecting signal is activated before the data which are transmitted from the memory cell MC to the bit lines BLT, BLC are fully amplified, the read operation is carried out properly. Therefore, it is suitable for high speed operation.
The input/output node ND01 is connected to a write data line WDT via a column switch 16a. The input/output node ND02 is connected to a write data line WDC via a column switch 16b. The input/output node ND03 is connected to a read data line RDT via the column switch 16c. The input/output node ND04 is connected to a read data line RDC via the column switch 16d. Gates of the column switches 16a to 16d receive a column selecting signal CSLP. The write data lines WDT, WDC are connected to a write amplifier (not shown) which receives write data from input/output terminals. The read data lines RDT, RDC are connected to a read amplifier (not shown) which outputs read data to the input/output terminals.
FIG. 2 shows an example of the operation of the aforementioned sense amplifier 10. In this example, the read data or the write data is transmitted to the bit line BLT. The bit line BLC (reference) acts as a line for supplying the reference voltage.
(A) Read Cycle
First, the memory cell array 14 on the left side of FIG. 1 is selected according to the supply of a row address signal, and the bit line control signal BTRP is inactivated (low level) (FIG. 2(a)). The not-shown bit line control signal BTRP is activated, and the memory cell array 14 and the bit lines BLT, BLC are connected. The voltages of the bit lines BLT, BLC are turned to the reference voltages in advance by the precharge operation (FIG. 2(b)).
Before the word line signal WLT is activated, the control signal BLPLCN is changed from a high level to a low level (kick operation). The control signal BLPLTN is maintained at the low level during the read operation. The voltage of the bit line BLC decreases by the action of the coupling capacitance of the capacitance 10c as the control signal BLPLCN changes (FIG. 2(c)).
Next, the word line signal WLT is activated according to the row address signal. It should be mentioned that activation levels of the word line signals WLT, WLC and the bit line control signals BTLP, BTRP are set to become higher than high level voltages of other signals (boost voltage). The transfer transistor of the memory cell MC is turned on by the activation of the word line signal WLT. Data held in the memory cell MC (in this example, in the H state) is transmitted to the bit line BLT, and the voltage of the bit line BLT increases (FIG. 2(d)). Incidentally, among the waveforms of the bit line BLT, the broken line which shifts toward the low level side shows when the memory cell MC maintaining the L state is read out.
The capacitance 10b is designed so that the voltage difference between the bit line pair BLT, BLC after the activation of the word line signal WLT becomes almost the same in the H state and in the L state by, for example, the aforementioned kick operation (FIG. 2(e)). Being thus designed, the read margin in the H state improves as compared with the case without the kick operation (FIG. 2(f)).
Thereafter, the latch 10a is activated, and the voltage difference between the bit line pair BLT, BLC increases. The read control signal RDRVN is activated in synchronization with the activation of the latch 10a (low level), and logic levels of the nodes ND03, ND04 and logic levels of the bit lines BLT, BLC are opposite to each other.
Next, the column selecting signal CSLP is activated (FIG. 2(g)), and voltages of the nodes ND03, ND04 are transmitted to the read data lines RDT, RDC, respectively. Thereafter, the column selecting signal CSLP and the word line signal WLT are inactivated (FIG. 2(h)), whereby the latch 10a is inactivated and an amplification period is complete.
Thereafter, the control signal BLPLCN and the bit line control signal BTRP are changed to the high levels. The bit lines BLT, BLC are equalized to each other, the read control signal RDRVN is inactivated (high level) and the read switches 10f, 10g are inactivated so that the read operation is complete.
(B) Write Cycle
When a word line is selected, data in the memory cells which are connected to the same word line are respectively transmitted to the bit line. In the write operation, data in the memory cells into which the data are not written are also transmitted to the bit line. In order to hold these data in the memory cells, rewrite operation (refresh operation) is necessary. Hence, the write operation of the memory cell into which the data is written is shown on the upper side of the drawing, and the rewrite operation of the memory cell into which the data is not written is shown on the lower side of the drawing.
In the write operation, the bit line control signal BTRP is inactivated (low level), similarly to the aforementioned read cycle (FIG. 2(i)). Next, the control signal BLPLCN is changed from the high level to the low level before the word line signal WLT is activated (kick operation). The voltage of the bit line BLC decreases by the coupling capacitance of the capacitance 10c as the control signal BLPLCN changes (FIG. 2(j)).
The word line signal WLT is activated and the transfer transistor of the memory cell MC is turned on. Data held in the memory cell MC (in this example, in the H state) is transmitted to the bit line BLT, and the voltage of the bit line BLT increases (FIG. 2(k)). The latch 10a is activated and the voltage difference between the bit line pair BLT, BLC increases. The write control signal WSELP and the column selecting signal CSLP are activated sequentially (FIG. 2(l)), the write data which are transmitted to the write data lines WDT, WDC are transmitted to the bit lines BLT, BLC via the nodes ND01, ND02, and the levels of the bit lines BLT, BLC are inverted (FIG. 2(m)).
Next, the column selecting signal CSLP and the write control signal WSELP are inactivated sequentially. The write data is amplified substantially by the latch 10a and written in the memory cell MC and thereafter, the word line signal WLT is inactivated (FIG. 2(n)). Thereafter, the control signal BLPLCN is changed to the high level. The bit line control signal BTRP is activated and the bit lines BLT, BLC are equalized to each other so that the write operation is complete.
In the rewrite operation, timings of the signals to be supplied to the sense amplifier 10 are the same as those in the above-described write operation, except for the column selecting signal CSLP. In the rewrite operation, the column selecting signal CSLP is not activated, and hence the data transmitted from the memory cell MC is amplified as it is by the latch 10a to be written in the memory cell MC again. Therefore, waveforms of the bit lines BLT, BLC are the same as those in the read cycle. As a result, it is also possible to improve the read margin of the memory cell MC in the H state in the rewrite operation. In other words, the amplified data is securely rewritten in the memory cell MC maintaining the H state.
FIG. 3 shows another example of the operation of the aforementioned sense amplifier 10. In this example, the read data or the write data is also transmitted to the bit line BLT. The bit line BLC (reference) acts as the line for supplying the reference voltage. The control signals BLPLTN, BLPLCN are usually maintained at the low levels, and one of the control signals is changed to the high level during the operation of the sense amplifier. Detailed explanations about the waveforms with the same timings as those in FIG. 2 are omitted.
(A) Read Cycle
First, the bit line control signal BTRP is inactivated and thereafter, the control signal BLPLTN is changed from the low level to the high level before the word line signal WLT is activated (kick operation). The control signal BLPLCN is maintained at the low level during the read operation. The voltage of the bit line BLT increases by the action of the coupling capacitance of the capacitance 10b as the control signal BLPLTN changes (FIG. 3(a)). Thereafter, the read operation is carried out similarly to FIG. 2.
Among the waveforms of the bit line BLT, the broken line which shifts toward the low level side shows when the memory cell MC maintaining the L state is read out. The capacitance 10c is designed so that the voltage difference between the bit line pair BLT, BLC after the activation of the word line signal WLT becomes almost the same in the H state and in the L state by, for example, the aforementioned kick operation (FIG. 3(b)). Therefore, the read margin in the H state improves as compared with the case without the kick operation (FIG. 3(c)).
(B) Write Cycle
The write operation is shown on the upper side of the drawing and the rewrite operation is shown on the lower side of the drawing. The write operation is the same as that in FIG. 2 except that the bit line BLT is subjected to the kick operation. In the rewrite operation, timings of the signals to be supplied to the sense amplifier 10 are the same as those in the write operation, except for the column selecting signal CSLP. Waveforms of the bit lines BLT, BLC are the same as those in the read cycle. As a result, it is also possible to improve the read margin of the memory cell MC in the H state in the rewrite operation.
However, in order to perform the aforesaid kick operation, it is necessary to prepare the capacitances 10b, 10c for each bit line pair BLT, BLC. Since the number of the bit lines is very large, the areas of the capacitances 10b, 10c are enormous. Further, wirings of the control signals BLPLTN, BLPLCN which control the capacitances 10b, 10c are lengthened. As a result, there are disadvantages that the size of a chip increases and the manufacturing cost increases.
It is an object of the present invention to decrease the size of a chip of a semiconductor memory having a sense amplifier.
It is another object of the present invention to decrease the number of elements of the sense amplifier and to operate the sense amplifier without fail.
According to one of the aspects of the present invention, a semiconductor memory comprises a bit line connected to a memory cell and a sense amplifier for amplifying a signal quantity of data transmitted to the bit line. The sense amplifier includes a transistor for electrically connecting, to the bit line, a data bus (an input/output node of data read from/written in the memory cell) to transmit the data. The transistor is operated not only during data amplification of the sense amplifier but also in advance prior to the data amplification. Along with the operation of the transistor, a voltage of the bit line is changed by a coupling capacitance of the transistor and the bit line. Namely, the voltage of the bit line is shifted before the data held in the memory cell is transmitted to the bit line (kick operation). Thus, it is possible to improve read margins of read data being either in an H state or in an L state without the formation of a capacitance dedicated for the kick operation. As a result, the size of the chip can be decreased.
According to another aspect of the present invention, the transistor connects one of its source or drain to the input/output node and the other of the source or drain to the bit line, respectively, and receives a write control signal which is activated during a write operation, at its gate. Namely, the voltage of the bit line can be changed by using the transistor which transmits write data to the bit line.
According to another aspect of the present invention, the transistor connects its drain to the input/output node and its gate to the bit line, and receives a read control signal which turns to a source voltage during a read operation, at its source. Namely, the voltage of the bit line can be changed by using the transistor which transmits the data read from the memory cell to the exterior.
According to another aspect of the present invention, a bit line pair is composed of two bit lines. The data and a reference voltage are respectively supplied to one of the bit lines and the other of the bit lines in accordance with an address signal supplied from the exterior. The transistors respectively connected to each of the bit lines of the bit line pair are controlled independently. Therefore, the voltage of at least one of the bit lines of the bit line pair can be easily changed by using the coupling capacitance of the transistors, without largely changing the circuits of the sense amplifier. As a result, potentials of the bit line pair can be differentiated in advance before the amplification of the sense amplifier, thereby improving the read margin.
According to another aspect of the present invention, the transistor connected to the bit line supplied with the reference voltage is operated in advance before the amplification. By this operation, a voltage of the bit line supplied with the reference voltage becomes lower than a voltage of the bit line supplied with the data. Thus, the voltages of the bit line pair can be differentiated in advance before the amplification of the sense amplifier.
According to another aspect of the present invention, the transistor connected to the bit line supplied with the data is operated in advance before the amplification. By this operation, the voltage of the bit line supplied with the data becomes higher than the voltage of the bit line supplied with the reference voltage. Thus, the voltages of the bit line pair can be differentiated in advance before the amplification of the sense amplifier.
According to another aspect of the present invention, the semiconductor memory further comprises a column switch for connecting the input/output node to the data line for inputting/outputting the data to/from the exterior. The column switch is operated in accordance with a column address signal for selecting the bit line. The transistor is operated in accordance with a row address signal for selecting a word line controlling the memory cell. The column switch inputs/outputs the data corresponding to the memory cell which is selected by the word line. Hence, the column switch is generally turned on after the amplification of the data is started. In other words, the column switch is off when the transistor is operated before the amplification. Therefore, it is possible to prevent the voltage of the bit line from being affected by a data line due to the operation of the transistor before the amplification. As a result, the data held in the memory cell can be read out more securely.